2018-01-09 07:44:39 +08:00
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/*******************************************************************************
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*
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* Filename: main.c
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*
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* Description: Main functions for Irext STM8 module driver
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*
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* Created by strawmanbobi 2017-12-31
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* Copyright (c) 2017 Irext. All rights reserved.
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*
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*******************************************************************************/
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#include <string.h>
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#include "stm8s.h"
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#include "stdlib.h"
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#include "stdio.h"
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#include "main.h"
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#ifdef _RAISONANCE_
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#define PUTCHAR_PROTOTYPE int putchar (char c)
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#define GETCHAR_PROTOTYPE int getchar (void)
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#elif defined (_COSMIC_)
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#define PUTCHAR_PROTOTYPE char putchar (char c)
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#define GETCHAR_PROTOTYPE char getchar (void)
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#else /* _IAR_ */
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#define PUTCHAR_PROTOTYPE int putchar (int c)
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#define GETCHAR_PROTOTYPE int getchar (void)
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#endif /* _RAISONANCE_ */
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#define TIM4_PERIOD 124
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#define UART_RECV_STOP 200
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/* UART related definition */
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#define REQ_READY 0x50
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#define REQ_WRITE 0x51
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#define REQ_ERR 0x52
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#define REQ_READ 0x53
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#define REQ_CATEGORY 0x54
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2018-01-18 07:53:40 +08:00
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#define REQ_COMMAND 0x55
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2018-01-09 07:44:39 +08:00
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#define RSP_READY 0x60
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#define RSP_INDEX 0x61
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#define RSP_LENGTH 0x62
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#define RSP_DATA 0x63
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#define RSP_DONE 0x64
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#define RSP_INDEX_DONE 0x65
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#define RSP_CMD_ERR 0x66
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2018-01-18 07:53:40 +08:00
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#define RSP_IR_OPENED 0x67
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#define RSP_IR_FAILURE 0x68
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2018-01-09 07:44:39 +08:00
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#define BLOCK_BYTES 16
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/* prototypes */
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static decode_control_block_t dccb =
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{
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.ir_type = IR_TYPE_NONE,
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.ir_state = IR_STATE_STANDBY,
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.source_code_length = 0,
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.decoded_length = 0
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};
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static t_remote_ac_status ac_status =
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{
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.ac_power = AC_POWER_OFF,
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.ac_temp = AC_TEMP_24,
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.ac_mode = AC_MODE_COOL,
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.ac_wind_dir = AC_SWING_ON,
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.ac_wind_speed = AC_WS_AUTO,
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.ac_display = 0,
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.ac_sleep = 0,
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.ac_timer = 0,
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};
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/* global variables */
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#if defined UART_DEFRAGMENT
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uint8_t receive_state = 0;
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uint8_t receive_buffer[1024] = { 0 };
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uint32_t received = 0;
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uint32_t uart_recv_stop_cd = UART_RECV_STOP;
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#endif
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/* local functions */
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static void IRext_processUartMsg();
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static void HandleBinReady();
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static void HandleBinWrite();
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static void HandleBinCategory();
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2018-01-18 07:53:40 +08:00
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static void HandleCommand();
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static void PrepareDecoding();
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2018-01-09 07:44:39 +08:00
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static void ParseCommand(uint8_t* data, uint16_t len);
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static void TransportDataToUart(uint8_t* data, uint16_t len);
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static void WriteBytes(uint8_t *data, uint16_t len);
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2018-01-19 19:22:57 +08:00
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2018-01-09 07:44:39 +08:00
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#if defined UART_DEFRAGMENT
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static void start_uart_cd(__IO uint32_t nTime);
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static void stop_uart_receive();
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#endif
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/* local vars */
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2018-01-19 19:22:57 +08:00
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/* test mode */
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#if defined TEST_MODE
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#define TEST_BIN_SIZE 568
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const uint8_t ac_code[568] =
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{
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0x1D, 0x00, 0x00, 0x09, 0x00, 0x10, 0x00, 0x18, 0x00, 0xFF, 0xFF, 0x33, 0x00, 0xFF, 0xFF, 0x34,
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0x00, 0x58, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0x76, 0x00, 0x7E, 0x01, 0xA6, 0x01, 0xCC, 0x01, 0xFF, 0xFF, 0xDC, 0x01, 0xE9, 0x01, 0xF6,
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0x01, 0xF8, 0x01, 0xFA, 0x01, 0xFC, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0x33, 0x31, 0x30, 0x30, 0x2C,
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0x39, 0x31, 0x30, 0x30, 0x35, 0x30, 0x30, 0x2C, 0x35, 0x30, 0x30, 0x35, 0x30, 0x30, 0x2C, 0x31,
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0x35, 0x30, 0x30, 0x36, 0x26, 0x35, 0x36, 0x30, 0x2C, 0x32, 0x35, 0x30, 0x30, 0x2C, 0x33, 0x30,
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0x30, 0x30, 0x2C, 0x39, 0x30, 0x30, 0x30, 0x7C, 0x2D, 0x31, 0x26, 0x35, 0x30, 0x30, 0x31, 0x30,
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0x30, 0x31, 0x30, 0x30, 0x31, 0x42, 0x32, 0x30, 0x36, 0x43, 0x30, 0x30, 0x38, 0x33, 0x32, 0x30,
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0x39, 0x41, 0x46, 0x30, 0x41, 0x37, 0x31, 0x30, 0x42, 0x30, 0x30, 0x30, 0x43, 0x31, 0x31, 0x30,
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0x44, 0x43, 0x30, 0x30, 0x45, 0x30, 0x32, 0x39, 0x32, 0x30, 0x46, 0x30, 0x30, 0x30, 0x30, 0x30,
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0x30, 0x46, 0x30, 0x30, 0x31, 0x31, 0x32, 0x41, 0x46, 0x37, 0x31, 0x30, 0x30, 0x31, 0x31, 0x46,
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0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30, 0x30, 0x34, 0x43, 0x35,
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0x30, 0x30, 0x46, 0x35, 0x38, 0x35, 0x43, 0x30, 0x32, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30,
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0x46, 0x34, 0x43, 0x35, 0x30, 0x30, 0x45, 0x35, 0x38, 0x35, 0x43, 0x30, 0x33, 0x30, 0x39, 0x34,
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0x30, 0x34, 0x34, 0x30, 0x30, 0x34, 0x43, 0x35, 0x30, 0x30, 0x46, 0x35, 0x38, 0x35, 0x43, 0x30,
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0x34, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30, 0x46, 0x34, 0x43, 0x35, 0x30, 0x30, 0x45, 0x35,
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0x38, 0x35, 0x43, 0x30, 0x35, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30, 0x46, 0x34, 0x43, 0x35,
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0x30, 0x30, 0x45, 0x35, 0x38, 0x35, 0x43, 0x30, 0x36, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x430,
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0x45, 0x34, 0x43, 0x35, 0x30, 0x30, 0x45, 0x35, 0x38, 0x35, 0x43, 0x30, 0x37, 0x30, 0x39, 0x34,
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0x30, 0x34, 0x34, 0x30, 0x30, 0x34, 0x43, 0x35, 0x30, 0x30, 0x46, 0x35, 0x38, 0x35, 0x43, 0x30,
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0x38, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30, 0x46, 0x34, 0x43, 0x35, 0x30, 0x30, 0x45, 0x35,
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0x38, 0x35, 0x43, 0x30, 0x39, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30, 0x46, 0x34, 0x43, 0x35,
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0x30, 0x30, 0x45, 0x35, 0x38, 0x35, 0x43, 0x30, 0x41, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30,
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0x45, 0x34, 0x43, 0x35, 0x30, 0x30, 0x45, 0x35, 0x38, 0x35, 0x43, 0x30, 0x42, 0x30, 0x39, 0x34,
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0x30, 0x34, 0x34, 0x30, 0x46, 0x34, 0x43, 0x35, 0x30, 0x30, 0x45, 0x35, 0x38, 0x35, 0x43, 0x30,
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0x43, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30, 0x45, 0x34, 0x43, 0x35, 0x30, 0x30, 0x45, 0x35,
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0x38, 0x35, 0x43, 0x30, 0x44, 0x30, 0x39, 0x34, 0x30, 0x34, 0x34, 0x30, 0x45, 0x34, 0x43, 0x35,
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0x30, 0x30, 0x45, 0x35, 0x38, 0x35, 0x43, 0x30, 0x45, 0x30, 0x33, 0x36, 0x30, 0x36, 0x34, 0x30,
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0x31, 0x30, 0x33, 0x36, 0x30, 0x36, 0x34, 0x30, 0x34, 0x30, 0x33, 0x36, 0x30, 0x36, 0x34, 0x30,
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0x30, 0x30, 0x33, 0x36, 0x30, 0x36, 0x34, 0x30, 0x33, 0x30, 0x33, 0x36, 0x30, 0x36, 0x34, 0x30,
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0x32, 0x30, 0x33, 0x36, 0x34, 0x36, 0x38, 0x30, 0x31, 0x30, 0x33, 0x36, 0x34, 0x36, 0x38, 0x30,
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0x35, 0x30, 0x36, 0x36, 0x34, 0x36, 0x38, 0x30, 0x39, 0x35, 0x38, 0x35, 0x43, 0x30, 0x38, 0x30,
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0x33, 0x36, 0x34, 0x36, 0x38, 0x30, 0x42, 0x30, 0x33, 0x34, 0x38, 0x34, 0x43, 0x30, 0x41, 0x30,
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0x33, 0x34, 0x38, 0x34, 0x43, 0x30, 0x46, 0x54, 0x26, 0x30, 0x2C, 0x31, 0x7C, 0x53, 0x26, 0x31,
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0x2C, 0x32, 0x2C, 0x33, 0x54, 0x26, 0x30, 0x2C, 0x31, 0x7C, 0x53, 0x26, 0x31, 0x2C, 0x32, 0x2C,
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0x33, 0x4E, 0x41, 0x4E, 0x41, 0x4E, 0x41, 0x31
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};
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#endif
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2018-01-09 07:44:39 +08:00
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void main(void)
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{
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CLK_HSIPrescalerConfig(CLK_PRESCALER_HSIDIV1);
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2018-01-19 19:22:57 +08:00
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#if defined TEST_MODE
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2018-01-09 07:44:39 +08:00
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// Init GPIO
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init_GPIO();
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2018-01-19 19:22:57 +08:00
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// Init UART
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init_UART();
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int i = 0;
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2018-01-09 07:44:39 +08:00
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2018-01-19 19:22:57 +08:00
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dccb.ir_state = IR_STATE_READY;
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dccb.ir_type = IR_TYPE_AC;
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dccb.source_code_length = TEST_BIN_SIZE;
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memset(dccb.source_code, BINARY_SOURCE_SIZE_MAX, 0x00);
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for (i = 0; i < dccb.source_code_length; i++)
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{
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dccb.source_code[i] = ac_code[i];
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}
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printf("decoding ac\n");
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PrepareDecoding();
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while(1)
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{
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;
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}
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#else
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// Init GPIO
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init_GPIO();
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2018-01-09 07:44:39 +08:00
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// Init UART
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init_UART();
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// Init Timer
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// init_Timer4();
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while (1)
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{
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#if defined UART_DEFRAGMENT
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start_uart_cd(UART_RECV_STOP);
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#endif
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IRext_processUartMsg();
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}
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2018-01-19 19:22:57 +08:00
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#endif
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2018-01-09 07:44:39 +08:00
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}
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void init_UART()
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{
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UART3_DeInit();
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2018-01-18 07:53:40 +08:00
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UART3_Init((uint32_t)115200, UART3_WORDLENGTH_8D, UART3_STOPBITS_1, UART3_PARITY_NO,
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2018-01-09 07:44:39 +08:00
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UART3_MODE_TXRX_ENABLE);
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#if defined UART_INT
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// enable UART3 RX interrupt
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UART3_ITConfig(UART3_IT_RXNE_OR, ENABLE);
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#endif
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}
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2018-01-19 19:22:57 +08:00
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/* initialization */
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void deinit_GPIO()
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{
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}
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void init_GPIO()
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{
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GPIO_Init(IR_IO_PORT, (GPIO_Pin_TypeDef)(IR_PIN), GPIO_MODE_OUT_PP_HIGH_FAST);
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}
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2018-01-09 07:44:39 +08:00
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void init_Timer4()
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{
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/* TIM4 configuration:
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- TIM4CLK is set to 16 MHz, the TIM4 Prescaler is equal to 128 so the TIM1 counter
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clock used is 16 MHz / 128 = 125 000 Hz
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- With 125 000 Hz we can generate time base:
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max time base is 2.048 ms if TIM4_PERIOD = 255 --> (255 + 1) / 125000 = 2.048 ms
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min time base is 0.016 ms if TIM4_PERIOD = 1 --> ( 1 + 1) / 125000 = 0.016 ms
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- In this example we need to generate a time base equal to 1 ms
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so TIM4_PERIOD = (0.001 * 125000 - 1) = 124 */
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/* Time base configuration */
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TIM4_TimeBaseInit(TIM4_PRESCALER_128, TIM4_PERIOD);
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/* Clear TIM4 update flag */
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TIM4_ClearFlag(TIM4_FLAG_UPDATE);
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/* Enable update interrupt */
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TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE);
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}
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#if defined UART_DEFRAGMENT
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static void start_uart_cd(__IO uint32_t nTime)
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{
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TIM4_Cmd(DISABLE);
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uart_recv_stop_cd = nTime;
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/* enable interrupts */
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enableInterrupts();
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/* Enable TIM4 */
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TIM4_Cmd(ENABLE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void stop_uart_receive()
|
|
|
|
|
{
|
|
|
|
|
// it seems there is no data from peer of uart, reset the receiving FSM
|
|
|
|
|
memset(receive_buffer, 1024, 0x00);
|
|
|
|
|
received = 0;
|
|
|
|
|
printf("UART receiving stopped\n");
|
|
|
|
|
TIM4_Cmd(DISABLE);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
void timer4_callback()
|
|
|
|
|
{
|
|
|
|
|
#if defined UART_DEFRAGMENT
|
|
|
|
|
if (uart_recv_stop_cd != 0)
|
|
|
|
|
{
|
|
|
|
|
uart_recv_stop_cd--;
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
stop_uart_receive();
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* UART TX/RX */
|
|
|
|
|
PUTCHAR_PROTOTYPE
|
|
|
|
|
{
|
|
|
|
|
UART3_SendData8(c);
|
|
|
|
|
while (UART3_GetFlagStatus(UART3_FLAG_TXE) == RESET);
|
|
|
|
|
|
|
|
|
|
return (c);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
GETCHAR_PROTOTYPE
|
|
|
|
|
{
|
|
|
|
|
#ifdef _COSMIC_
|
|
|
|
|
char c = 0;
|
|
|
|
|
#else
|
|
|
|
|
int c = 0;
|
|
|
|
|
#endif
|
|
|
|
|
while (UART3_GetFlagStatus(UART3_FLAG_RXNE) == RESET);
|
|
|
|
|
c = UART3_ReceiveData8();
|
|
|
|
|
return (c);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* handle UART commands */
|
|
|
|
|
void IRext_uartFeedback()
|
|
|
|
|
{
|
|
|
|
|
if (dccb.decoded_length > 0)
|
|
|
|
|
{
|
|
|
|
|
for (uint16_t index = 0; index < dccb.decoded_length; index++)
|
|
|
|
|
{
|
|
|
|
|
WriteBytes((uint8_t*)&dccb.ir_decoded[index], 2);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void IRext_processUartMsg()
|
|
|
|
|
{
|
|
|
|
|
uint8_t data_received = 0;
|
|
|
|
|
|
|
|
|
|
data_received = getchar();
|
|
|
|
|
switch(data_received)
|
|
|
|
|
{
|
|
|
|
|
case REQ_READY:
|
|
|
|
|
HandleBinReady();
|
|
|
|
|
break;
|
|
|
|
|
case REQ_WRITE:
|
|
|
|
|
HandleBinWrite();
|
|
|
|
|
break;
|
|
|
|
|
case REQ_CATEGORY:
|
|
|
|
|
HandleBinCategory();
|
|
|
|
|
break;
|
2018-01-18 07:53:40 +08:00
|
|
|
case REQ_COMMAND:
|
|
|
|
|
HandleCommand();
|
2018-01-09 07:44:39 +08:00
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void HandleBinReady()
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
Request for ready
|
|
|
|
|
+------+
|
|
|
|
|
| 0x50 |
|
|
|
|
|
+------+
|
|
|
|
|
*/
|
|
|
|
|
dccb.decoded_length = 0;
|
|
|
|
|
memset(dccb.source_code, BINARY_SOURCE_SIZE_MAX, 0x00);
|
2018-01-18 07:53:40 +08:00
|
|
|
dccb.recv_index = 0;
|
2018-01-09 07:44:39 +08:00
|
|
|
dccb.source_code_length = 0;
|
|
|
|
|
putchar(RSP_READY);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void HandleBinWrite()
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
Request for write IR binary
|
|
|
|
|
+-------------------------------------------------------------+
|
|
|
|
|
| 0x51 | exp_idx (1 byte) | exp_len (1 byte) | data (n bytes) |
|
|
|
|
|
+-------------------------------------------------------------+
|
|
|
|
|
*/
|
|
|
|
|
uint8_t expected_index = 0;
|
|
|
|
|
uint8_t expected_length = 0;
|
|
|
|
|
uint16_t received = 0;
|
|
|
|
|
|
|
|
|
|
// receive bin block index
|
|
|
|
|
expected_index = getchar();
|
|
|
|
|
// prepare the offset for the next write
|
2018-01-18 07:53:40 +08:00
|
|
|
dccb.recv_index = expected_index << 4;
|
2018-01-09 07:44:39 +08:00
|
|
|
|
|
|
|
|
// receive expected length of next transfer
|
|
|
|
|
expected_length = getchar();
|
|
|
|
|
|
|
|
|
|
if (expected_length == 0 || expected_length > BLOCK_BYTES)
|
|
|
|
|
{
|
|
|
|
|
// error occurred!
|
|
|
|
|
putchar(RSP_CMD_ERR);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
for(received = 0; received < expected_length; received++)
|
|
|
|
|
{
|
|
|
|
|
dccb.source_code[dccb.recv_index + received] = getchar();
|
|
|
|
|
}
|
2018-01-18 07:53:40 +08:00
|
|
|
dccb.source_code_length = dccb.recv_index + received;
|
2018-01-09 07:44:39 +08:00
|
|
|
putchar(RSP_INDEX_DONE);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void HandleBinCategory()
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
Request for write category
|
|
|
|
|
+----------------------+
|
|
|
|
|
| 0x54 | cate (1 byte) |
|
|
|
|
|
+----------------------+
|
|
|
|
|
*/
|
|
|
|
|
dccb.ir_type = (ir_type_t)getchar();
|
|
|
|
|
// bin transfer done
|
|
|
|
|
putchar(RSP_DONE);
|
2018-01-18 07:53:40 +08:00
|
|
|
PrepareDecoding();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void HandleCommand()
|
|
|
|
|
{
|
|
|
|
|
/*
|
|
|
|
|
Request for write category
|
|
|
|
|
+----------------------+
|
|
|
|
|
| 0x55 | cate (1 byte) |
|
|
|
|
|
+----------------------+
|
|
|
|
|
*/
|
|
|
|
|
|
2018-01-09 07:44:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void ParseCommand(uint8_t* data, uint16_t len)
|
|
|
|
|
{
|
|
|
|
|
uint8_t ir_type = 0;
|
|
|
|
|
uint8_t key_code = 0;
|
|
|
|
|
uint8_t ac_function = 0;
|
|
|
|
|
|
|
|
|
|
if (IR_STATE_OPENED != dccb.ir_state)
|
|
|
|
|
{
|
|
|
|
|
// feek back error state
|
|
|
|
|
WriteBytes("11", 2);
|
|
|
|
|
return;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
ir_type = data[0];
|
|
|
|
|
|
|
|
|
|
if (IR_TYPE_TV == dccb.ir_type && 0x31 == ir_type)
|
|
|
|
|
{
|
|
|
|
|
// decode as TV
|
|
|
|
|
key_code = data[1] - 0x30;
|
|
|
|
|
dccb.decoded_length = ir_decode(key_code, dccb.ir_decoded, NULL, 0);
|
|
|
|
|
}
|
|
|
|
|
else if (IR_TYPE_AC == dccb.ir_type && 0x32 == ir_type)
|
|
|
|
|
{
|
|
|
|
|
ac_function = data[1] - 0x30;
|
|
|
|
|
dccb.decoded_length = ir_decode(ac_function, dccb.ir_decoded, &ac_status, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (dccb.decoded_length > 0)
|
|
|
|
|
{
|
|
|
|
|
IRext_uartFeedback();
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2018-01-18 07:53:40 +08:00
|
|
|
static void PrepareDecoding()
|
|
|
|
|
{
|
|
|
|
|
// parse IREXT binary automatically
|
|
|
|
|
if (IR_TYPE_TV == dccb.ir_type)
|
|
|
|
|
{
|
|
|
|
|
if (IR_DECODE_SUCCEEDED ==
|
|
|
|
|
ir_binary_open(IR_CATEGORY_TV, 1, dccb.source_code, dccb.source_code_length))
|
|
|
|
|
{
|
|
|
|
|
dccb.ir_state = IR_STATE_OPENED;
|
|
|
|
|
putchar(RSP_IR_OPENED);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
putchar(RSP_IR_FAILURE);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else if (IR_TYPE_AC == dccb.ir_type)
|
|
|
|
|
{
|
|
|
|
|
if (IR_DECODE_SUCCEEDED ==
|
|
|
|
|
ir_binary_open(IR_CATEGORY_AC, 1, dccb.source_code, dccb.source_code_length))
|
|
|
|
|
{
|
|
|
|
|
dccb.ir_state = IR_STATE_OPENED;
|
|
|
|
|
putchar(RSP_IR_OPENED);
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
putchar(RSP_IR_FAILURE);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
else
|
|
|
|
|
{
|
|
|
|
|
putchar(RSP_IR_FAILURE);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2018-01-09 07:44:39 +08:00
|
|
|
static void TransportDataToUart(uint8_t* data, uint16_t len)
|
|
|
|
|
{
|
|
|
|
|
for (uint16_t i = 0; i < len; i++)
|
|
|
|
|
{
|
|
|
|
|
delay(10);
|
|
|
|
|
putchar(data[i]);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
static void WriteBytes(uint8_t *data, uint16_t len)
|
|
|
|
|
{
|
|
|
|
|
TransportDataToUart(data, len);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* helper functions */
|
|
|
|
|
#ifdef USE_FULL_ASSERT
|
|
|
|
|
void assert_failed(uint8_t* file, uint32_t line)
|
|
|
|
|
{
|
|
|
|
|
while (1)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
void delay(u16 count)
|
|
|
|
|
{
|
|
|
|
|
u8 i, j;
|
|
|
|
|
while (count--)
|
|
|
|
|
{
|
|
|
|
|
for(i = 0; i < 50; i++)
|
|
|
|
|
for(j = 0; j < 20; j++);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|